An 8-bit 160 MS/s folding-interpolating ADC with optimized active averaging/interpolating network

An 8-bit CMOS folding-interpolating analog-to-digital converter is presented. A new method for designing an optimized averaging circuit is also described. Careful circuit design and layout leads to a high-speed (160 MSPS) and low power (70 mW in 2.5 V supply voltage) ADC. The ADC is successfully implemented in 0.25 /spl mu/m CMOS digital process and it takes 1/spl times/1.4 mm/sup 2/ silicon area.